Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store instructions and data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.
Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors. Even slower has been the increase in operating speed of memory controllers coupling processors to memory devices. The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.
In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay of several clock periods. Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices.
One approach to alleviating the memory latency problem is to use multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, a system controller or memory controller is coupled to several memory modules, each of which includes a memory hub coupled to several memory devices. The memory hub efficiently routes memory requests and responses between the controller and the memory devices. Computer systems employing this architecture can have a higher bandwidth because a processor can access one memory device while another memory device is responding to a prior memory access. For example, the processor can output write data to one of the memory devices in the system while another memory device in the system is preparing to provide read data to the processor. Although computer systems using memory hubs may provide superior performance, they nevertheless often fail to operate at optimum speed for several reasons. For example, even though memory hubs can provide computer systems with a greater memory bandwidth, they still suffer from latency problems of the type described above. More specifically, although the processor may communicate with one memory device while another memory device is preparing to transfer data, it is sometimes necessary to receive data from one memory device before the data from another memory device can be used. In the event data must be received from one memory device before data received from another memory device can be used, the latency problem continues to slow the operating speed of such computer systems.
One technique that has been used to reduce latency in memory devices is a cache memory, which stores data recently accessed from system memory. The cache memory is generally in the form of a static random access memory (“SRAM”), which has a substantially shorter access time compared to dynamic random access memory (“DRAM”) typically used as system memory. Furthermore, the SRAM cache memory is generally coupled directly to the processor through a processor bus rather than through a system controller or the like as is typical with DRAM system memory. As a result of the faster speed of cache memory and the closer proximity of cache memory to the processor, the use of cache memory can greatly reduce the latency of memory read operations.
Although conventional cache memory has reduced memory access latencies in conventional computer systems, cache memory has not been used in a manner that provides optimum performance in computer systems using memory hubs. In particular, the limited storage capacity of typical cache memories compared to the vastly larger capacity of typical memory hub system memories makes cache memory of lesser value since a cache hit is less likely to occur. This problem is exacerbated by the difficulty in transferring data to cache memory that is likely to be the subject of subsequent memory requests. More specifically, it is difficult to couple the data that will subsequently be needed from all of the memory modules through the memory controller to the processor and then from the processor to the cache memory. Also, it can be difficult to maintain cache coherency in a computer system using memory hubs and a cache memory coupled to the processor through the processor bus, and it can require significant hardware resources to maintain cache coherency. Furthermore, the time required to maintain cache coherency can slow memory performance to the extent that much of the performance advantages of using cache memory can be lost.
There is therefore a need for a computer architecture that provides the advantages of a memory hub architecture and also minimize this latency problems common in such systems, thereby providing a memory devices with high bandwidth and low latency.